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74LV132D

nexperia
Part Number 74LV132D
Manufacturer nexperia
Description Quad 2-input NAND Schmitt trigger
Published Dec 27, 2020
Detailed Description 74LV132 Quad 2-input NAND Schmitt trigger Rev. 8 — 13 September 2021 Product data sheet 1. General description The 74L...
Datasheet PDF File 74LV132D PDF File

74LV132D
74LV132D

Overview
74LV132 Quad 2-input NAND Schmitt trigger Rev.
8 — 13 September 2021 Product data sheet 1.
General description The 74LV132 is a quad 2-input NAND gate with Schmitt-trigger inputs.
Inputs include clamp diodes.
This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.
2.
Features and benefits • Wide supply voltage range from 1.
0 V to 5.
5 V • CMOS low power dissipation • Optimized for low voltage applications: 1.
0 V to 3.
6 V • Accepts TTL input levels between VCC = 2.
7 V and VCC = 3.
6 V • Typical output ground bounce < 0.
8 V at VCC = 3.
3 V and Tamb = 25 °C • Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.
3 V and Tamb = 25 °C • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B • Complies with JEDEC standards: • JESD8-7 (1.
65 V to 1.
95 V) • JESD8-5 (2.
3 V to 2.
7 V) • JESD8C (2.
7 V to 3.
6 V) • JESD36 (4.
5 V to 5.
5 V) • ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-A exceeds 200 V • Multiple package options • Specified from -40 °C to +85 °C and from -40 °C to +125 °C 3.
Applications • Wave and pulse shapers for highly noisy environments • Astable multivibrators • Monostable multivibrators 4.
Ordering information Table 1.
Ordering information Type number Package Temperature range Name Description 74LV132D -40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.
9 mm 74LV132PW -40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
4 mm 74LV132BQ -40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.
5 × 3 × 0.
85 mm Version SOT108-1 SOT402-1 SOT762-1 Nexperia 5.
Functional diagram 1 1A 2 1B 1Y 3 4 2A 5 2B 2Y 6 9 3A 10 3B 3Y 8 12 4A 13 4B Fig.
1.
Logic symbol 4Y 11 mna407 1 & 3 2 4 & 6 5 9 & 8 10 12 & 11 13 mna408 Fig.
2.
IEC logic symbol 6.
Pinning information 74LV132 Quad 2-input NAND Schmitt tr...


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