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74LV595D

nexperia
Part Number 74LV595D
Manufacturer nexperia
Description 8-bit serial-in/serial-out or parallel-out shift register
Published Dec 27, 2020
Detailed Description 74LV595 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 5 — 29 September 2021 Product data sh...
Datasheet PDF File 74LV595D PDF File

74LV595D
74LV595D

Overview
74LV595 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev.
5 — 29 September 2021 Product data sheet 1.
General description The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.
Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input.
A LOW on MR will reset the shift register.
Data is shifted on the LOW-to-HIGH transitions of the SHCP input.
The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.
If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
A HIGH on OE causes the outputs to assume a high-impedance OFF-state.
Operation of the OE input does not affect ...


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