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IDT72V71643

Renesas
Part Number IDT72V71643
Manufacturer Renesas
Description 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH
Published Dec 30, 2020
Detailed Description 3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE IDT72V71643 MATCHING 4,096 x 4,096 PRODUCT DISCONTINUATION ...
Datasheet PDF File IDT72V71643 PDF File

IDT72V71643
IDT72V71643


Overview
3.
3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE IDT72V71643 MATCHING 4,096 x 4,096 PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES JULY 31, 2015 FEATURES: • Up to 32 serial input and output streams • Maximum 4,096 x 4,096 channel non-blocking switching • Accepts data streams at 2.
048 Mb/s, 4.
096 Mb/s, 8.
192 Mb/s or 16.
384 Mb/s • Internal Loopback for testing • Available in 144-pin Thin Quad Flatpack (TQFP) and 144-pin Ball Grid Array (BGA) packages • Operating Temperature Range -40°C to +85°C • 3.
3V I/O with 5V tolerant inputs and TTL compatible outputs • Rate matching capability: Mux/Demux mode and Split mode • Output Enable Indication Pins • Per-channel Variable Delay mode for low-latency applications DESCRIPTION: The IDT72V71643 has a maximum non-blocking switch capacity of • Per-channel Constant Delay mode for frame integrity applications 4,096x4,096channelswithdatarates at 2.
048Mb/s,4.
096Mb/s,8.
192 Mb/s • Automatic identification of ST-BUS® and GCI serial streams • Automatic frame offset delay measurement or 16.
384 Mb/s.
With 32 inputs and 32 outputs, a variety of rate combinations is supported, under either Mux/Demux mode or Split mode, to allow for • Per-stream frame delay offset programming • Per-channel high-impedance output control • Per-channel Processor mode to allow microprocessor writes to switching between streams of different data rates.
Output enable indications are provided through optional pins (one pin per output stream, only 16 output streams can be used in this mode) to facilitate TX streams external data bus control.
• Direct microprocessor access to all internal memories For applications requiring 32 streams and 32 per-stream Output Enable • Memory block programming for quick setup • IEEE-1149.
1 (JTAG) Test Port indicators, there is also an All Output Enable Feature.
FUNCTIONAL BLOCK DIAGRAM Vcc GND RESET TMS TDI TDO TCK TRST ODE RX0 RX1 RX2 RX3 RX4 RX5 RX6 RX7 RX8 RX9 RX10 RX11 RX12 RX13 RX14 RX15 RX16...


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