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74ALVCH16601DGG

Part Number	74ALVCH16601DGG
Manufacturer	nexperia
Description	18-bit universal bus transceiver
Published	Jan 4, 2021
Detailed Description	74ALVCH16601 18-bit universal bus transceiver; 3-state Rev. 3 — 13 August 2018 Product data sheet 1. General descripti...
Datasheet	74ALVCH16601DGG PDF File

Overview

74ALVCH16601 18-bit universal bus transceiver; 3-state Rev.
3 — 13 August 2018 Product data sheet 1.
General description The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level.
If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB.
When OEAB is LOW, the outputs are active.
When OEAB is HIGH, the outputs are in the high-impedance state.
The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
To ensure the high impedance state during power up or powe...

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74ALVCH16601DGG 18-bit universal bus transceiver - nexperia

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