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ISL55162

Elevate
Part Number ISL55162
Manufacturer Elevate
Description SOC Dual Channel 300MHz Pin Electronics/DAC/PMU/Deskew
Published Apr 2, 2021
Detailed Description ISL55162 SOC Dual Channel 300MHz Pin Electronics/DAC/ PMU/Deskew ISL55162 • Deskew The ISL55162 is a highly integrat...
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ISL55162
ISL55162

Overview
ISL55162 SOC Dual Channel 300MHz Pin Electronics/DAC/ PMU/Deskew ISL55162 • Deskew The ISL55162 is a highly integrated System-on-a-Chip (SOC) pin electronics solution aimed at incorporating every analog - Propagation Delay Adjustment - Falling Edge Adjustment function, along with some digital support circuitry, required on a - Delay Range set by PLL Clock per channel basis for Automated Test Equipment.
The interface, • On-Chip DC Levels control and I/O of the chip are all digital; all analog circuitry is inside the chip.
Two complete tester channels are integrated into - 11 Levels/Channel each chip.
- Gain and Offset Correction/Level - DUT Ground Sensing and Correction ISL55162 is pin and functionally compatible with Venus, Venus Plus and Venus 2.
• 3-Bit Serial CPU Port • Flexible High Speed Digital Inputs and Outputs CONFIDENTIAL Features • Pin Electronics Driver/Comparator - 3 Level Driver (DVH/DVL/VTT) - Selectable On-Chip Terminations for Inputs - 50: Series Termination for Comparator Outputs • Lead Free Package - 8V Driver Output Swings - 64-Lead, 10mmx10mm TQFP with Top Exposed Heat Slug - 16V Comparator Input Voltage Range - Pdq < 1.
1W/Channel - Extremely Low HiZ Leakage over 16V Range • Per Pin PMU - FV, FI, MV, MI - 4 Quadrant Operation Applications • Automated Test Equipment • Instrumentation - 8 Current Ranges (32mA, 8mA, 2mA, 512PA, 128PA, 32PA, 8mA, 2PA) • ASIC Verifiers - +13V Super Voltage Capability - FI Voltage Clamps - Resistive Load (8 selectable resistor values) 2 DATA_0 2 EN_0 DVH-0 DVL-0 VTT-0 2 COMP_B_0 2 COMP_A_0 V-FI-0 V-FV-0 V-Cl-Hi-0 V-Cl-Lo-0 F/S PMU V-MU January 8, 2016 MONITOR EXT_FORCE EXT_SENSE DOUT_0 DOUT_1 - CVB-0 + + - CVA-0 CVB-1 CVA-1 - CVA-PPMU-0 CVA-PPMU-1 + + - CVB-PPMU-0 CVB-PPMU-1 FIGURE 1.
BLOCK DIAGRAM 1 + + - + + - DVH-1 DVL-1 VTT-1 2 DATA_1 2 EN_1 2 COMP_B_1 2 COMP_A_1 F/S PMU V-MU V-FI-1 V-FV-1 V-Cl-Hi-1 V-Cl-Lo-1 www.
elevatesemi.
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