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AX11015

ASIX
Part Number AX11015
Manufacturer ASIX
Description Single Chip Microcontroller
Published May 13, 2021
Detailed Description Features AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Document No: AX11015/V1.09/0...
Datasheet PDF File AX11015 PDF File

AX11015
AX11015

Overview
Features AX11015 Single Chip Microcontroller with TCP/IP and 10/100M Fast Ethernet MAC/PHY Document No: AX11015/V1.
09/06/14/2011 MCU 8-bit pipelined RISC, single cycle per instruction with maximum operating frequency of 100Mhz (100 MIPS) 100% software compatible with standard 8051/80390 4 GPIO ports of 8 bits 2 external interrupt sources with 2 priority levels Support power management unit, programmable watchdog timer, and 3 16-bit timer/counters Debug port for connecting to In-Circuit Emulation (ICE) adaptor 5 channels of programmable counter array On-chip Program and Data Memory Embed 512KB Flash memory, and 16KB SRAM for program code mirroring.
The external program memory can grow up to 2MB without bank select Support initial Flash memory programming via UART or ICE adaptor, the so-called In System Programming (ISP) Support reprogrammable boot code and In Application Programming (IAP) to update run-time firmware or boot code through Ethernet or UART (US Patent Pending) Support boot loader to shadow program code on to internal 16KB SRAM and external SRAM for high performance applications Embed 32KB SRAM for data memory, expandable up to 2MB via external SRAM without bank select Buffer Management Innovative-shared memory architecture to allow external program and data memory to share the same SRAM memory chip with flexible memory space allocation Embed DMA engine and memory arbiter.
Support 5 DMA channels for high performance data movement needed for network protocol stack processing On-chip 10/100M Fast Ethernet MAC and PHY Integrate IEEE 802.
3 10BASE-T/100BASE-TX compatible Fast Ethernet MAC and PHY with dedicated 12KB SRAM for Ethernet packet buffering.
Support full-duplex and half-duplex operations.
Provide optional MII interface (for HomePNA and HomePlug) Support twisted pair crossover detection and auto-correction (HP Auto-MDIX) Support wakeup via Link-up, Magic packet, Wakeup frame, external input pin or UART TCP/IP Build in TCP/IP accelerat...


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