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HD74LS190P

Renesas
Part Number HD74LS190P
Manufacturer Renesas
Description Synchronous Up / Down Decade Counter
Published Jul 25, 2021
Detailed Description HD74LS190 Synchronous Up / Down Decade Counter (signal clock line) REJ03D0452–0200 Rev.2.00 Jul.15.2005 Synchronous ope...
Datasheet PDF File HD74LS190P PDF File

HD74LS190P
HD74LS190P

Overview
HD74LS190 Synchronous Up / Down Decade Counter (signal clock line) REJ03D0452–0200 Rev.
2.
00 Jul.
15.
2005 Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic.
This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four master-slave flip-flops are triggered on a low-to-high-level transition of the clock input if the enable input is low.
A high at the enable input inhibits counting.
Level changes at the enable input should be made only when the clock input is high.
The direction of the count is determined by the level of the down / up input.
When low, the counter counts up and when high, it counts down.
Level changes at the down / up input should be made only when the clock input is high.
This counter is fully programmable; that is, the outputs may be preset to either level by placing a low on the load input and entering the desired data at the data inputs.
The output will change to agree with the data inputs independently of the level of the clock input.
This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
The clock, down / up, and load inputs are buffered to lower the drive requirement which significantly reduces the number of clock drivers, etc.
, required for long parallel words.
Two outputs have been made available to perform the cascading function: ripple clock and maximum / minimum count.
The latter output produces a high-level output pulse with a duration approximately equal to one complete cycles to the clock when the counter overflows or underflows.
The ripple clock output produces a low-level output pulse equal in width to the low-level portion of the clock input when an overflow or underflow conditions exists.
The counters can be easily cascaded by feeding the ripple clock o...


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