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HD74LS374P

Renesas
Part Number HD74LS374P
Manufacturer Renesas
Description Octal D-type Edge-triggered Flip-Flops
Published Jul 25, 2021
Detailed Description HD74LS374 Octal D-type Edge-triggered Flip-Flops (with three-state outputs) REJ03D0483–0200 Rev.2.00 Feb.18.2005 The H...
Datasheet PDF File HD74LS374P PDF File

HD74LS374P
HD74LS374P

Overview
HD74LS374 Octal D-type Edge-triggered Flip-Flops (with three-state outputs) REJ03D0483–0200 Rev.
2.
00 Feb.
18.
2005 The HD74LS374, 8-bit register features totem-pole three-state outputs designed specifically for driving highlycapacitive or relatively low-impedance loads.
The high-impedance third state and increased high-logic-level drive provide this register with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components.
They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops are edge-triggered D-type flipflops.
On the positive transition the clock, the Q outputs will be set to the logic states that ware setup at the D inputs.
Features • Ordering Information Part Name Package Type Package Code Package (Previous Code) Abbreviation HD74LS374P DILP-20 pin PRDP0020AC-B (DP-20NEV) P HD74LS374FPEL SOP-20 pin (JEITA) PRSP0020DD-B (FP-20DAV) FP HD74LS374RPEL SOP-20 pin (JEDEC) PRSP0020DC-A RP (FP-20DBV) Note: Please consult the sales office for the above package availability.
Taping Abbreviation (Quantity) — EL (2,000 pcs/reel) EL (1,000 pcs/reel) Pin Arrangement Output Control 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 Q OE CK D CK D OE Q Q OE CK D CK D OE Q OE Q CK D CK D OE Q OE Q CK D CK D OE Q 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 Clock (Top view) Rev.
2.
00, Feb.
18.
2005, page 1 of 7 HD74LS374 Function Table Inputs Output control Clock D L ↑ H L ↑ L L L X H X X Notes: H; high level, L; low level, X; irrelevant ↑; transition from low to high level Q0; level of Q before the indicated steady state input conditions were established Z; off (high-impedance) state of a three state output Block Diagram 1Q 2Q 3Q 4Q 5Q 6Q 7Q Outputs Q H L Q0 Z 8Q Q Q Q Q Q Q Q Q D CK D CK D CK D CK D CK D CK D CK D CK Ou...


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