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CD54HC573F3A

Texas Instruments
Part Number CD54HC573F3A
Manufacturer Texas Instruments
Description OCTAL TRANSPARENT D-TYPE LATCHES
Published Aug 25, 2021
Detailed Description CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS454A – FEBRUARY 2001 – REVISED APRIL 2003...
Datasheet PDF File CD54HC573F3A PDF File

CD54HC573F3A
CD54HC573F3A

Overview
CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS454A – FEBRUARY 2001 – REVISED APRIL 2003 D 2-V to 6-V VCC Operation D Wide Operating Temperature Range of –55°C to 125°C D 3-State Outputs Directly Drive Bus Lines D Balanced Propagation Delays and Transition Times D Bus Driver Outputs Drive Up To 15 LS-TTL Loads D Significant Power Reduction Compared to LS-TTL Logic ICs description/ordering information CD54HC573 .
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F PACKAGE CD74HC573 .
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E OR M PACKAGE (TOP VIEW) OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE The ’HC573 devices are octal transparent D-type latches designed for 2-V to 6-V VCC operation.
When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state.
In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect the internal operations of the latches.
Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74HC573E CD74HC573E Tube –55°C to 125°C SOIC – M Tape and reel CD74HC573M CD74HC573M96 HC573M CDIP – F Tube CD54HC573F3A CD54HC573F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.
ti.
com/sc...


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