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SN74AUC16374

Texas Instruments
Part Number SN74AUC16374
Manufacturer Texas Instruments
Description 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
Published Aug 31, 2021
Detailed Description www.ti.com FEATURES • Member of the Texas Instruments Widebus™ Family • Optimized for 1.8-V Operation and Is 3.6-V I/O T...
Datasheet PDF File SN74AUC16374 PDF File

SN74AUC16374
SN74AUC16374

Overview
www.
ti.
com FEATURES • Member of the Texas Instruments Widebus™ Family • Optimized for 1.
8-V Operation and Is 3.
6-V I/O Tolerant to Support Mixed-Mode Signal Operation • Ioff Supports Partial-Power-Down Mode Operation • Sub-1-V Operable • Max tpd of 2.
8 ns at 1.
8 V • Low Power Consumption, 20-µA Max ICC • ±8-mA Output Drive at 1.
8 V • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 16-bit edge-triggered D-type flip-flop is operational at 0.
8-V to 2.
7-V VCC, but is designed specifically for 1.
65-V to 1.
95-V VCC operation.
The SN74AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
It can be used as two 8-bit flip-flops or one 16-bit flip-flop.
On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
SN74AUC16374 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCES403E – JULY 2002 – REVISED APRIL 2007 DGG OR DGV PACKAGE (TOP VIEW) 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2OE 24 48 1CLK 47 1D1 46 1D2 45 GND 44 1D3 43 1D4 42 VCC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 36 2D1 35 2D2 34 GND 33 2D3 32 2D4 31 VCC 30 2D5 29 2D6 28 GND 27 2D7 26 2D8 25 2CLK A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE does not affect internal operations of the latch.
Old data can be retained or new da...


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