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8432I-101

Renesas
Part Number 8432I-101
Manufacturer Renesas
Description Differential-to-3.3V LVPECL Frequency Synthesizer
Published Oct 28, 2021
Detailed Description 700MHz, Differential-to-3.3V LVPECL Frequency Synthesizer 8432I-101 Data Sheet GENERAL DESCRIPTION The 8432I-101 is a ...
Datasheet PDF File 8432I-101 PDF File

8432I-101
8432I-101


Overview
700MHz, Differential-to-3.
3V LVPECL Frequency Synthesizer 8432I-101 Data Sheet GENERAL DESCRIPTION The 8432I-101 is a general purpose, dual outp u t D i f fe r e n t i a l - t o - 3 .
3 V LV P E C L h i g h f r e q u e n c y synthesizer and a member of the family of High Performance Clock Solutions from IDT.
The 8432I-101 has a selectable TEST_CLK or CLK, nCLK inputs.
The TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.
3V LVPECL levels.
The CLK, nCLK pair can accept most standard differential input levels.
The VCO operates at a frequency range of 250MHz to 700MHz.
The VCO frequency is programmed in steps equal to the value of the input differential or single ended reference frequency.
The VCO and output frequency can be programmed using the serial or parallel interfaces to the configuration logic.
The low phase noise characteristics of the 8432I-101 makes it an ideal clock source for Gigabit Ethernet and SONET applications.
FEATURES • Dual differential 3.
3V LVPECL outputs • Selectable CLK, nCLK or LVCMOS/LVTTL TEST_CLK • TEST_CLK can accept the following input levels: LVCMOS or LVTTL • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK, nCLK or TEST_CLK maximum input frequency: 40MHz • Output frequency range: 25MHz to 700MHz • VCO range: 250MHz to 700MHz • Accepts any single-ended input signal on CLK input with resis- tor bias on nCLK input • Parallel interface for programming counter and output dividers • RMS period jitter: 5ps (maximum) • Cycle-to-cycle jitter: 25ps (maximum) • 3.
3V supply voltage • -40°C to 85°C ambient operating temperature • Available in lead-free (RoHS 6) package BLOCK DIAGRAM PIN ASSIGNMENT nCLK nP_LOAD VCO_SEL M0 M1 M2 M3 M4 ©2016 Integrated Device Technology, Inc 32 31 30 29 28 27 26 25 M5 1 24 CLK M6 2 23 TEST_CLK M7 3 22 CLK_SEL M8 4 N0 5 ICS8432I-101 21 VCCA 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK VEE 8 17 MR 9 10 11 12 13 14 15 1...



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