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CD74ACT109

Texas Instruments
Part Number CD74ACT109
Manufacturer Texas Instruments
Description DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
Published May 31, 2023
Detailed Description CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 D Input...
Datasheet PDF File CD74ACT109 PDF File

CD74ACT109
CD74ACT109


Overview
CD54ACT109, CD74ACT109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS327 – JANUARY 2003 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54ACT109 .
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F PACKAGE CD74ACT109 .
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E OR M PACKAGE (TOP VIEW) 1CLR 1 1J 2 1K 3 1CLK 4 1PRE 5 1Q 6 1Q 7 GND 8 16 VCC 15 2CLR 14 2J 13 2K 12 2CLK 11 2PRE 10 2Q 9 2Q description/ordering information The ’ACT109 devices contain two independent J-K positive-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse.
Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs.
These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D-type flip-flops if J and K are tied together.
ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74ACT109E CD74ACT109E –55°C to 125°C SOIC – M Tube CD74ACT109M Tape and reel CD74ACT109M96 ACT109M CDIP – F Tube CD54ACT109F3A CD54ACT109F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.
ti.
com/sc/package.
FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H† H† H H ↑ L L L H H H ↑ H L Toggl...



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