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CD54ACT112

Texas Instruments
Part Number CD54ACT112
Manufacturer Texas Instruments
Description DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
Published May 31, 2023
Detailed Description CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 D Input...
Datasheet PDF File CD54ACT112 PDF File

CD54ACT112
CD54ACT112

Overview
CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 CD54ACT112 .
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F PACKAGE CD74ACT112 .
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M PACKAGE (TOP VIEW) 1CLK 1 1K 2 1J 3 1PRE 4 1Q 5 1Q 6 2Q 7 GND 8 16 VCC 15 1CLR 14 2CLR 13 2CLK 12 2K 11 2J 10 2PRE 9 2Q description/ordering information The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs.
When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge...


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