CDCVF2505-Q1
www. ti. com. . SCAS867 – DECEMBER 2008
3. 3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER
FEATURES
1
• Qualified for Automotive Applications • Phase-Locked Loop Clock Driver for
Synchronous DRAM and General-Purpose Applications
• Spread-Spectrum Clock Compatible • Operating Frequency: 24 MHz to 200 MHz • Low Jitter (Cycle-to-Cycle): <150 ps Over the
Range 66 MHz to 200 MHz
• Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay)
• Three-States Outputs When There Is No Input Clock
• Operates From Single 3. 3-V Supply • Available in 8-Pin SOIC Package
• Consumes Less Than 100 µA (Typically) in Power Down Mode
• Internal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock
• 25-Ω On-Chip Series Damping Resistors • Integrated RC PLL Loop Fi...
CDCVF2505-Q1 PDF File
