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CEC1734

Microchip

Real Time Platform Root of Trust Controllers

CEC173x Real Time Platform Root of Trust Controllers Operating Conditions • Operating Voltage: 3.3 V • Interface Voltag...


CEC1734

Microchip


Octopart Stock #: O-1522278

Findchips Stock #: 1522278-F

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Description
CEC173x Real Time Platform Root of Trust Controllers Operating Conditions • Operating Voltage: 3.3 V • Interface Voltages: 3.3 V and optional 1.8 V SPI • Operating Temperature Range: -40 oC to 85 oC Low Power Modes • Chip is designed to always operate in Lowest Power state during Normal Operation • Supports 2 Chip-level Sleep Modes: Light Sleep an
More View d Heavy Sleep - Low Standby Current in Sleep Modes ARM® Cortex-M4F Embedded Processor • Programmable clock frequency up to 96 MHz • Floating point processor • Single 4GByte Addressing Space • Nested Vectored Interrupt Controller (NVIC) - Maskable Interrupt Controller - Maskable hardware wake up events - 8 Levels of priority, individually assignable by vector • EC Interrupt Aggregator expands number of Inter- rupt sources supported or reduces number of vectors needed • Complete ARM® Standard debug support - JTAG-Based DAP port, comprised of SWJ- DP and AHB-AP debugger access functions • MPU Feature (Memory Protection Unit) Memory Components • SRAM 384 KB Total - Code: 320 KB; Data: 64 KB - Two independent partitions allow for execution with no wait states • 8Kbit One Time Programmable (OTP) Memory - In circuit programmable without additional BOM components • ROM - Contains Boot ROM - Contains Real Time APIs for built-in functions • In-package SPI Serial Flash - 2MBytes for 64-pin Single SPI Channel - 4MBytes for 84-pin Dual SPI Channel Clocks • 96 MHz Internal PLL • Internal 32 kHz silicon oscillator clock source Package Options • 84-pin WFBGA, dual SPI channel monitors • 64-pin VFBGA, single SPI channel monitor Security Features • Boot ROM Secure Boot Loader - CNSA Compliant (SHA-384/ECC384) - Meets NIST 800-193 PFR Guidelines - Supports 2 Code Images in internal SPI Flash (Primary and Fall-back image) - Authenticates SPI Flash image before loading - Support AES-256 Encrypted SPI Flash images • SPI Boot Flash Monitoring and Intervention - Dual Channel: BMC and CPU (in 84-pin) - Allows 50 MHz operation of SPI Flash - Real Time load module verification and execution path matching during Host boot - Prevents unauthorized Read/Write/Erase during Host runtime - Isolates Host from Flash devices using internal QSPI Analog switches - Each SPI Monitor block has its own 64KB Match patterns for comparison with SPI Channel data - Performs Hash calculation on 8KB match region • Hardware Accelerators: - Multi purpose AES Crypto Engine: - Support for 128-bit - 256-bit key length - Cryptographic Hash Engine - SHA-2: SHA-256, SHA-384, SHA-512 - Public Key Crypto Engine - Hardware support for RSA and Elliptic Curve asymmetric public key algorithms - RSA keys length of 1024 to 4096 bits - ECC Prime Field keys up to 521 bits - ECC Binary Field keys up to 571 bits - Microcoded support for standard public key algorithms - ECDSA - KC-ECDSA - Ed25519 • Hardware Physically Unclon






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