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RC19016

Part Number	RC19016
Manufacturer	Renesas
Description	PCIe Gen5/6 Fanout Buffer
Published	Dec 10, 2023
Detailed Description	RC190xx PCIe Gen5/6 Fanout Buffer Family with LOS Datasheet The RC190xx (RC19024, RC19020, RC19020A072, RC19016, RC190...
Datasheet	RC19016 PDF File

Overview

RC190xx PCIe Gen5/6 Fanout Buffer Family with LOS Datasheet The RC190xx (RC19024, RC19020, RC19020A072, RC19016, RC19013, RC19008, RC19004, and RC19002) ultra-high performance fanout buffers support PCIe Gen5 and Gen6.
They provide a LossOf-Signal (LOS) output for system monitoring and redundancy.
The devices also incorporate Power Down Tolerant (PDT) and Flexible Startup Sequencing (FSS) features, easing system design.
They can drive both source-terminated and doubleterminated loads, operating up to 400MHz.
The family offers 2, 4, 8, 13, 16, 20, and 24 LowPower (LP) HCSL output pairs in 3 × 3 mm to 10 × 10 mm packages.
The RC190xx devices offer higher output counts in smaller packages compared to earlier buffer families.
The buffers support both Common Clock (CC) and Independent Reference (IR) PCIe clock architectures.
Applications ▪ Cloud/High-performance computing ▪ nVME storage ▪ Networking ▪ Accelerators Features ▪ PCIe Gen5 additive phase jitter: 6fs RMS ▪ PCIe Gen6 additive phase jitter: 4fs RMS ▪ DB2000Q additive phase jitter: 10fs RMS ▪ 12kHz to 20MHz additive phase jitter: 30fs RMS at 156.
25MHz ▪ Power Down Tolerant (PDT) inputs ▪ Flexible Startup Sequencing (FSS) ▪ Automatic Clock Parking (ACP) upon loss of CLKIN ▪ Spread-spectrum tolerant ▪ CLKIN accepts HCSL or LVDS signal levels ▪ -40 to +105°C, 3.
3V ±10% operation ▪ All devices except RC19002: • Selectable output slew rate via pin/SMBus • 4-wire Side-Band Interface supports high-speed serial output enable and device daisy-chaining • 9 SMBus addresses plus write protection • 85Ω or 100Ω (A100 suffix) output impedance • Pin-selectable slew rate ▪ RC19002: Pin-selectable output impedance C LKI Nb CLKIN Note 3 SADR_tri[1 :0] SC LK SDATA PWR GD _PW R DN b Note 1, 3 SLE WRATE_ SEL Note 2, 3 Note 3 OEb [m:n] SBI _I N SBI_CLK SHFT_ LDb SBI_ENQ Clock Dete ct Control Logic SM Bus Inte rface Output Co ntro l Side-Ban d Inte rface LOS b CLKb2 3 CLK23 24 20 16 13 8 4 or 2 outputs CLKb0 CLK0 Note 2, 3 S...

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