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ACT5261

Aeroflex Circuit Technology
Part Number ACT5261
Manufacturer Aeroflex Circuit Technology
Description ACT 5261 64-Bit Superscaler Microprocessor
Published Mar 23, 2005
Detailed Description ACT 5261 64-Bit Superscaler Microprocessor Features s s Full militarized QED RM5261 microprocessor Dual Issue superscal...
Datasheet PDF File ACT5261 PDF File

ACT5261
ACT5261

Overview
ACT 5261 64-Bit Superscaler Microprocessor Features s s Full militarized QED RM5261 microprocessor Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle q 133, s High-performance floating point unit: up to 500 MFLOPS q Single 150, 200, 250 MHz operating frequencies – Consult Factory for latest speeds q 345 Dhrystone 2.
1 MIPS q SPECInt95 7.
3, SPECfp95 8.
3 s s cycle repeat rate for common single precision operations and some double precision operations q Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations q Single cycle repeat rate for single precision combined multiplyadd operation s Pinout compatible with popular RM5260 High performance system interface compatible with RM5260, RM 5270, RM5271, RM7000, R4600, R4700 and R5000 q 64-bit • MIPS IV instruction set q Floating multiplexed system address/data bus for optimum price/ performance q High performance write protocols maximize uncached write bandwidth q Supports 1/2 clock divisors (2, 2.
5, 3, 3.
5, 4, 4.
5, 5, 6, 7, 8, 9) q IEEE 1149.
1 JTAG boundary scan s point multiply-add instruction increases performance in signal processing and graphics applications q Conditional moves to reduce branch frequency q Index address modes (register + register) s Embedded application enhancements q Specialized • Integrated on-chip caches q 32KB q 32KB DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction q I and D cache locking by set q Optional dedicated exception vector for interrupts s instruction - 2 way set associative data - 2 way set associative q Virtually indexed, physically tagged q Write-back and write-through on per page basis q Pipeline restart on first double for data cache misses s Fully static CMOS design with power down logic q Standby q 3.
6 reduced power mode with WAIT instruction Watts typical power @ 200MHz q 2.
5V core with 3.
3V IO’s s s 208-lead CQFP, cavity-up package...


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