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KSZ8463FRL

Microchip
Part Number KSZ8463FRL
Manufacturer Microchip
Description 10/100 Managed Switch
Published Feb 4, 2024
Detailed Description KSZ8463ML/RL/FML/FRL IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII Fea...
Datasheet PDF File KSZ8463FRL PDF File

KSZ8463FRL
KSZ8463FRL


Overview
KSZ8463ML/RL/FML/FRL IEEE 1588 Precision Time Protocol-Enabled, Three-Port, 10/100 Managed Switch with MII or RMII Features Management Capabilities • The KSZ8463ML/RL/FML/FRL Includes All the Functions of a 10/100BASE-T/TX/FX Switch System that Combines a Switch Engine, Frame Buffer Management, Address Look-Up Table, Queue Management, MIB Counters, Media Access Controllers (MAC) and PHY Transceivers • Non-Blocking Store-and-Forward Switch Fabric Ensures Fast Packet Delivery by Utilizing 1024 Entry Forwarding Table • Port Mirroring/Monitoring/Sniffing: Ingress and/or Egress Traffic to any Port • MIB Counters for Fully Compliant Statistics Gathering: 34 Counters per Port • Loopback Modes for Remote Failure Diagnostics • Rapid Spanning Tree Protocol Support (RSTP) for Topology Management and Ring/Linear Recovery • Bypass Mode Ensures Continuity Even When a Host is Disabled or Fails Robust PHY Ports • Two Integrated IEEE 802.
3/802.
3u-Compliant Ethernet Transceivers Supporting 10BASE-T and 100BASE-TX • Copper and 100BASE-FX Fiber Mode Support in the KSZ8463FML and KSZ8463FRL • Copper Mode Support in the KSZ8463ML and KSZ8463RL • On-Chip Termination Resistors and Internal Biasing for Differential Pairs to Reduce Power • HP Auto MDI/MDI-X Crossover Support Eliminates the Need to Differentiate Between Straight or Crossover Cables in Applications MAC Ports • Three Internal Media Access Control (MAC) Units • MII or RMII Interface Support on MAC Port 3 • 2Kbyte Jumbo Packet Support • Tail Tagging Mode (One byte Added before FCS) Support at Port 3 to Inform The Processor Which Ingress Port Receives the Packet and its Priority • Supports Reduced Media Independent Interface (RMII) with 50 MHz Reference Clock Input or Output • Supports Media Independent Interface (MII) in Either PHY Mode or MAC Mode on Port 3 • Programmable MAC Addresses for Port 1 and Port 2 and Source Address Filtering for Implementing Ring Topologies • MAC Filtering Function to Filter or Forward Unknown Unic...


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