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IS61QDPB24M18C

ISSI
Part Number IS61QDPB24M18C
Manufacturer ISSI
Description 72Mb QUADP Synchronous SRAM
Published Feb 18, 2024
Detailed Description IS61QDPB24M18C/C1/C2 IS61QDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 2) Synchronous SRAM (2.5 CYCLE READ LATENCY) A...
Datasheet PDF File IS61QDPB24M18C PDF File

IS61QDPB24M18C
IS61QDPB24M18C

Overview
IS61QDPB24M18C/C1/C2 IS61QDPB22M36C/C1/C2 4Mx18, 2Mx36 72Mb QUADP (Burst 2) Synchronous SRAM (2.
5 CYCLE READ LATENCY) APRIL 2018 FEATURES  2Mx36 and 4Mx18 configuration available.
 On-chip Delay-Locked Loop (DLL) for wide data valid window.
 Separate independent read and write ports with concurrent read and write operations.
 Max.
450 MHz clock for high bandwidth  Synchronous pipeline read with EARLY write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 2.
5 Cycle read latency.
 Fixed 2-bit burst for read and write operations.
 Two input clocks (K and K#) for address and control registering at rising edges only.
 Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
 Data valid pin (QVLD).
 +1.
8V core power supply and 1.
5, 1.
8V VDDQ, used with 0.
75, 0.
9V VREF.
 HSTL input and output interface.
 Full data coherency.
 Boundary scan using limited set of JTAG 1149.
1 functions.
 Byte Write capability.
 Fine ball grid array ...


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