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IS64LPS25636B

ISSI
Part Number IS64LPS25636B
Manufacturer ISSI
Description 9Mb Single CYCLE DESELECT STATIC RAM
Published Feb 18, 2024
Detailed Description IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 256K x 36, 256K x 32...
Datasheet PDF File IS64LPS25636B PDF File

IS64LPS25636B
IS64LPS25636B

Overview
IS61LPS51218B, IS61LPS25636B, IS61LPS25632B, IS64LPS25636B, IS61VPS/VVPS51218B, IS61VPS/VVPS25636B 256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM MAY 2017 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth ex- pansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for BGA package • Power Supply LPS: Vdd 3.
3V (+ 5%), Vddq 3.
3V/2.
5V (+ 5%) VPS: Vdd 2.
5V (+ 5%), Vddq 2.
5V (+ 5%) VVPS: Vdd 1.
8V (+ 5%), Vddq 1.
8V (+ 5%) • JEDEC 100-Pin QFP, 119-ball BGA, and 165ball BGA packages • Lead-free available FAST ACCESS TIME Symbol Parameter tkq Clock Access Time tkc Cycle Time Frequency DESCRIPTION The 9Mb product family features  high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.
The IS61LPS/VPS25636B and IS64LPS25636B are organized as 262,144 words by 36 bits.
The IS61LPS25632B is organized as 262,144 words by 32 bits.
The IS61LPS/VPS51218B is organized as 524,288 words by 18 bits.
Fabricated with ISSI's ad- vanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input.
Write cycles can be one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write enable (BWE) input combined with one or more ...


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