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TMP87PM74FG

Toshiba
Part Number TMP87PM74FG
Manufacturer Toshiba
Description 8-Bit Microcontroller
Published Feb 20, 2024
Detailed Description TOSHIBA Original CMOS 8-Bit Microcontroller TLCS-870 Series TMP87PM74FG Semiconductor Company TMP87PM74 Important Notic...
Datasheet PDF File TMP87PM74FG PDF File

TMP87PM74FG
TMP87PM74FG

Overview
TOSHIBA Original CMOS 8-Bit Microcontroller TLCS-870 Series TMP87PM74FG Semiconductor Company TMP87PM74 Important Notices Thank you for your continued patronage of Toshiba microcontrollers.
This page gives you important information on using Toshiba microcontrollers.
Please be sure to check each item for proper use of our products.
2008-02-08 TOSHIBA Microcontrollers 870 Family (TMP87CH74A) (TMP87CM74A) (TMP87PM74) TMP87PM74 Datasheet Modifications: I2C Bus Mode Control The following problem is included in the explanation of the I2C bus function of this data sheet.
It will guide the correction as follows.
Please read it for the explanation of this data sheet as follows.
Section: “I2C Bus Mode Control” ▪ In the explanation of the Serial Bus Interface Control Register 1 1.
Delete the setting examples where the serial clock frequency exceeds 100 kHz.
2.
Add the following note.
SCK Serial clock selection 000 : Reserved 001 : Reserved 010 : 57.
1 011 : 29.
9 100 : 15.
3 101 : 7.
72 110 : 3.
88 111 : reserved (Note) (Note) kHz kHz kHz kHz kHz at fc = 8MHz (Output on SCL pin) Write only Note: This I2C bus circuit does not support the Fast mode.
It supports the Standard mode only.
Although the I2C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I2C specification is not guaranteed in that case.
▪ In “(3) Serial clock” 1.
Add the following sentence about the communication baud rate.
a.
Clock source The SCK (bits 2 to 0 in the SBICR1) is used to select a maximum transfer frequency outputed on the SCL pin in the master mode.
Set a communication baud rate that meets the I2C bus specification, such as the shortest pulse width of tLOW, based on the equations shown below.
Four or more machine cycles are required for both the high and low levels of the pulse width of a clock which is input externally in both the master and slave mode.
tLOW = 2n/fc tHIGH = 2n/fc + 12/fc fscl = 1/(tLow + tHIGH) 2008-02-08 TMP87PM74 Document Chang...


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