Part Number
|
M13S128324A |
Manufacturer
|
ESMT |
Description
|
Double Data Rate SDRAM |
Published
|
Apr 3, 2024 |
Datasheet
|
M13S128324A PDF File
|
Features
Double-data-rate architecture, two data transfers per clock cycle Bi-directional data strobe (DQS) Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 2.5, 3 ...
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