| Part Number | IDTCSPT855 |
| Manufacturer | Renesas |
| Title | 2.5V PHASE LOCKED LOOP CLOCK DRIVER |
| Description | The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four d... |
| Features |
• PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications • Spread spectrum clock compatible • Operating frequency: 60MHz to 220MHz • Low jitter (cycle-to-cycle): ±50ps • Distributes one differential clock input to four differential clock outputs • Enters low power mode and 3-stat... |
| File Size | 228.88KB |
| Datasheet |
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IDTCSPT855 : The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a highimpedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20MHz (typical 10MHz). An input frequency detection circuit detects the low-frequency condition, and after applying a .
IDTCSPT857 : IDTCSPT857/A • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications • Operating frequency: 60MHz to 200MHz • Standard speed: PC1600 (DDR200), PC2100 (DDR266) • A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333) • 1 to 10 differential clock distribution • Very low skew (100ps) • Very low jitter (75ps) • 2.5V AVDD and 2.5V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 48-pin TSSOP and 56-pin VFBGA packages The CSPT857 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ).
IDTCSPT857A : IDTCSPT857/A • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications • Operating frequency: 60MHz to 200MHz • Standard speed: PC1600 (DDR200), PC2100 (DDR266) • A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333) • 1 to 10 differential clock distribution • Very low skew (100ps) • Very low jitter (75ps) • 2.5V AVDD and 2.5V VDDQ • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 48-pin TSSOP and 56-pin VFBGA packages The CSPT857 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ).
IDTCSPT857C : IDTCSPT857C • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications • Operating frequency: 60MHz to 220MHz • Very low skew: – 100ps for PC1600 - PC2700 – 75ps for PC3200 • Very low jitter: – 75ps for PC1600 - PC2700 – 50ps for PC3200 • 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700 • 2.6V AVDD and 2.6V VDDQ for PC3200 • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56pin VFBGA packages The CSPT857C is a PLL based clock driver that acts as a zero delay buffer to distrib.
IDTCSPT857D : IDTCSPT857D • 1 to 10 differential clock distribution • Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications requiring improved output crosspoint voltage • Operating frequency: 60MHz to 220MHz • Very low skew: – 100ps for PC1600 - PC2700 – 75ps for PC3200 • Very low jitter: – 75ps for PC1600 - PC2700 – 50ps for PC3200 • 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700 • 2.6V AVDD and 2.6V VDDQ for PC3200 • CMOS control signal input • Test mode enables buffers while disabling PLL • Low current power-down mode • Tolerant of Spread Spectrum input clock • Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56pin VFBGA packages The CSPT857D is a PLL based clock drive.