DatasheetsPDF.com

IDTCSPT855

Part Number	IDTCSPT855
Manufacturer	Integrated Device Technology
Description	2.5V PHASE LOCKED LOOP CLOCK DRIVER
Published	Jun 23, 2010
Detailed Description	IDTCSPT855 2.5V PLL CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES www.DataSheet4U.com 2.5V PHASE LOCKED L...
Datasheet	IDTCSPT855 PDF File

Overview

IDTCSPT855 2.
5V PLL CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES www.
DataSheet4U.
com 2.
5V PHASE LOCKED LOOP CLOCK DRIVER IDTCSPT855 • PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications • Spread spectrum clock compatible • Operating frequency: 60MHz to 180MHz • Low jitter (cycle-to-cycle): ±50ps • Distributes one differential clock input to four differential clock outputs • Enters low power mode and 3-state outputs when input CLK signal is less than 20MHz or PWRDWN is low • Operates from dual 2.
5V supplies • Consumes <200µA quiescent current • External feedback pins (FBIN, FBIN) are used to synchronize outputs to input clocks • Available in TSSOP package FEATURES: DESCRIPTION: The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT).
When PWRDWN is high, the outputs switch in phase and frequency with CLK.
When PWRDWN is low, all outputs are disabled to a highimpedance state (3-state), and the PLL is shut down (low-power mode).
The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20MHz (typical 10MHz).
An input frequency detection circuit detects the low-frequency condition, and after applying a >20MHz input signal, this detection circuit reactivates the PLL and enables the outputs.
When AVDD is tied to GND, the PLL is turned off and bypassed for test purposes.
The CSPT855 is also able to track spread spectrum clocking for reducted EMI.
Since the CSPT855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up.
FUNCTIONAL BLOCK DIAGRAM 3 Y0 2 12 Y0 Y1 Y1 Y2 Y2 PWRDWN AVDD 24 9 POWERDOWN AND TEST LOGIC 13 17 16 26 Y3 27 Y3 FBOUT FBOUT CLK CLK FBIN FBIN 6 7...

Similar Datasheet

IDTCSPT855 2.5V PHASE LOCKED LOOP CLOCK DRIVER - Integrated Device Technology
IDTCSPT857 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER - Integrated Device Technology
IDTCSPT857A 2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER - Integrated Device Technology
IDTCSPT857C 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER - Integrated Device Technology
IDTCSPT857D 2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER - Integrated Device Technology

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)