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A67L8318

AMIC Technology
Part Number A67L8318
Manufacturer AMIC Technology
Description 256K X 16/18/ 128K X 32/36 LVTTL/ Pipelined DBA SRAM
Published Mar 23, 2005
Detailed Description A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary Document Title 256K X 16/18, 128K X 3...
Datasheet PDF File A67L8318 PDF File

A67L8318
A67L8318

Overview
A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary Document Title 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM Revision History Rev.
No.
0.
0 0.
1 LVTTL, Pipelined DBATM SRAM History Initial issue Change fast access time from 4.
0/4.
2/4.
5/5.
0 ns to 4.
5/5.
0/6.
0 ns Issue Date March 11, 1999 December 29, 1999 Remark Preliminary PRELIMINARY (December, 1999, Version 0.
1) AMIC Technology, Inc.
DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary Features n Fast access time: 4.
5/5.
0/6.
0 ns (117/100/83MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal +3.
3V ± 5% power supply n Individual Byte Write control capability n Clock enable ( CEN ) pin to enable clock and suspend operations n Clock-controlled and registered address, data and control signals n Registered output for pipelined applications n Three separate chip enables allow wide range of options for CE control, address pipelining n Internally self-timed write cycle n Selectable BURST mode (Linear or Interleaved) n SLEEP mode (ZZ pin) provided n Available in 100 pin LQFP package LVTTL, Pipelined DBATM SRAM General Description The AMIC Direct Bus Alternation™ (DBA™) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67L8316, A67L8318, A67L7332, A67L7336 SRAMs integrate a 256K X 16, 256K X 18, 128K X 32 or 128K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.
These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during WriteRead alternation.
The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers.
The synchronous inputs include all address, all data inputs, active low chip enable ( CE ), two additional chip enables for easy depth expansion (CE2, CE2...


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