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CS51312

Cherry Semiconductor Corporation
Part Number CS51312
Manufacturer Cherry Semiconductor Corporation
Description Synchronous CPU Buck Controller
Published Mar 24, 2005
Detailed Description CS51312 CS51312 Synchronous CPU Buck Controller for 12V Only Applications Description The CS51312 is a synchronous dual...
Datasheet PDF File CS51312 PDF File

CS51312
CS51312


Overview
CS51312 CS51312 Synchronous CPU Buck Controller for 12V Only Applications Description The CS51312 is a synchronous dual NFET Buck Regulator Controller.
It is designed to power the core logic of the latest high performance CPUs and ASICs from a single 12V input.
It uses TM the V2 control method to achieve the fastest possible transient response and best overall regulation.
It incorporates many additional features required to ensure the proper operation and protection of the CPU and Power system.
The CS51312 provides the industry’s most highly integrated solution, minimizing external component count, total solution size, and cost.
The CS51312 is specifically designed to power Intel’s Pentium® II processor and includes the following features: 5-bit DAC with 1.
2% tolerance, Power-Good output, overcurrent hiccup mode protection, overvoltage protection, VCC monitor, Soft Start, adaptive voltage positioning, adaptive FET non-overlap time, and remote sense.
The CS51312 will operate over a 9V to 20V (VCC2) range using either single or dual input voltage and is available in 16 lead narrow body surface mount package.
Features s Synchronous Switching Regulator Controller for CPU VCORE s Dual N-Channel MOSFET Synchronous Buck Design s V2 TM Control Topology s 200ns Transient Loop Response s 5 bit DAC with 1.
2% Tolerance s Hiccup Mode Overcurrent Protection s 40ns Gate Rise and Fall Times (3.
3nF load) s 65ns Adaptive FET Non-overlap Time s Adaptive Voltage Positioning s Power-Good Output Monitors Regulator Output s 5V/12V or 12V-only Operation s VCC Monitor Provides Under Voltage Lockout s OVP Output Monitors Regulator Output s Multifunction COMP Pin Provides ENABLE, Soft Start, and Hiccup Timing in Addition to Control Loop Compensation Application Diagram 12V C1 1.
0µF 12V D1 SS16GICT-ND C2 C3 C4 + + + R1 22Ω D2 ZM4746ACT-ND R2 200 C9 0.
01µF 220µF 16SV220 FY10AAJ-03A Q1 R3 FY10AAJ-03A Q2 FY10AAJ-03A 10 12 11 13 14 C6 0.
010µF C11 C12 C13 L1 1.
2µH R4 0.
004Ω + + + + + Pa...



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