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AT25F1024

ATMEL Corporation
Part Number AT25F1024
Manufacturer ATMEL Corporation
Description SPI Serial Memory
Published Mar 24, 2005
Detailed Description Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • 20 MHz Clock Rate • B...
Datasheet PDF File AT25F1024 PDF File

AT25F1024
AT25F1024

Overview
Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • 20 MHz Clock Rate • Byte Mode and 256-byte Page Mode for Program Operations • Sector Architecture: – Two Sectors with 32K Bytes Each (512K) – Four Sectors with 32K Bytes Each (1M) – 128 Pages per Sector • Product Identification Mode • Low-voltage Operation – 2.
7 (VCC = 2.
7V to 3.
6V) • Sector Write Protection • Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection • Self-timed Program Cycle (60 µs/Byte Typical) • Self-timed Sector Erase Cycle (1 second/Sector Typical) • Single Cycle Reprogramming (Erase and Program) for Status Register • High Reliability – Endurance: 10,000 Write Cycles Typical • Lead-free Devices Available • 8-lead JEDEC SOIC and 8-lead SAP Packages Description The AT25F512/1024 provides 524,288/1,048,576 bits of serial reprogrammable Flash memory organized as 65,536/131,072 words of 8 bits each.
The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.
The AT25F512/1024 is available in a space-saving 8-lead JEDEC SOIC and 8-lead SAP packages.
The AT25F512/1024 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK).
All write cycles are completely self-timed.
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array (1M) or entire memory array (512K) is enabled by programming the status register.
Separate write enable and write disable instructions are provided for additional data protection.
Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register.
The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
Pin Configurations 8-lead SOIC Pin Name CS SCK SI Function Chip Select Serial Data Clo...


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