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HV5408

Supertex Inc
Part Number HV5408
Manufacturer Supertex Inc
Description 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs
Published Mar 26, 2005
Detailed Description HV5308 HV5408 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs Ordering Information Package O...
Datasheet PDF File HV5408 PDF File

HV5408
HV5408

Overview
HV5308 HV5408 32-Channel Serial To Parallel Converter With High Voltage Push-Pull Outputs Ordering Information Package Options Device 44 J-Lead Quad Ceramic Chip Carrier HV5308DJ HV5408DJ 44 J-Lead Quad Plastic Chip Carrier HV5308PJ HV5408PJ 44 Lead Quad Plastic Gullwing HV5308PG HV5408PG Die HV5308X HV5408X 44 J-Lead Quad Ceramic Chip Carrier (MIL-STD-883 Processed*) RBHV5308DJ RBHV5408DJ HV5308 HV5408 * For Hi-Rel process flows, please refer to perfer to page 5-3 in the Databook.
Features ❏ Processed with HVCMOS® technology ❏ Low power level shifting ❏ Source/sink current minimum 20mA ❏ Shift register speed 8MHz ❏ Latched data outputs ❏ CMOS compatible inputs ❏ Forward and reverse shifting options ❏ Diode to VPP allows efficient power recovery General Description The HV53 and HV54 are low voltage serial to high voltage parallel converters with push-pull outputs.
These devices have been designed for use as drivers for AC-electroluminescent displays.
They can also be used in any application requiring multiple output high voltage current sourcing and sinking capabilities such as driving plasma panels, vacuum fluorescent, or large matrix LCD displays.
These devices consist of a 32-bit shift register, 32 latches, and control logic to enable outputs.
Q1 is connected to the first stage of the shift register through the Output Enable logic.
Data is shifted through the shift register on the low to high transition of the clock.
The HV54 shifts in the counterclockwise direction when viewed from the top of the package and the HV53 shifts in the clockwise direction.
A data output buffer is provided for cascading devices.
This output reflects the current status of the last bit of the shift register (32).
Operation of the shift register is not affected by the LE (latch enable) or the OE (output enable) inputs.
Transfer of data from the shift register to the latch occurs when the LE input is high.
The data in the latch is retained when LE is low.
Absolute Maximum Ratings1 Su...


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