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AN983B

ETC
Part Number AN983B
Manufacturer ETC
Description PCI/miniPCI-to-Ethernet LAN Controller
Published Mar 26, 2005
Detailed Description www.DataSheet4U.com AN983B/AN983BL PCI/miniPCI-to-Ethernet LAN Controller DATASHEET Rev. 1.8 MAY. 2003 DataShee DataS...
Datasheet PDF File AN983B PDF File

AN983B
AN983B

Overview
www.
DataSheet4U.
com AN983B/AN983BL PCI/miniPCI-to-Ethernet LAN Controller DATASHEET Rev.
1.
8 MAY.
2003 DataShee DataSheet4U.
com ADMtek.
com.
tw Information in this document is provided in connection with ADMtek products.
ADMtek may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined.
" ADMtek reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The products may contain design defects or errors known as errata, which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
To obtain latest documents, please contact your local ADMtek sales office or your distributor or visit ADMtek’s website at http://www.
ADMtek.
com.
tw *Third-party brands and names are the property of their respective owners.
DataSheet4U.
com www.
DataSheet4U.
com AN983B Datasheet Revision History Revision Date Oct, 2000 Feb, 2001 Mar, 2001 Revision 0.
1 1.
0 1.
1 PCI/miPCI Fast Ethernet Controller with integrated PHY Description Draft data sheet for review First release Add CSR15.
bit28 MRXCK Add CSR18.
bit26 PMEP Add CSR18.
bit27 PMEPEN Sep, 2001 Sep, 2001 Sep, 2001 1.
2 1.
3 1.
4 Add 25MHz crystal accuracy Revise PHY registers Revise product logo of Pin assignment diagram P.
17 MrxD0~D3 P.
23 CIOSA : 1 means enable ; 0 means disable P.
14 Add LED info to pin diagram JULY, 2002 1.
5 P.
25 Offset 80h, DID default value : 0981h P.
40 CSR18[25] / PWRS_clr : 1 means PCI_reset rising will clear CR49[1:0]/PWRS JULY, 2002 JULY, 2002 MAY, 2003 1.
6 1.
7 1.
8 P.
85 FIG21, FIG22, FIG23, FIG24 added for MII interface signal timing.
P.
45 Unicast registers added P.
69 Modify some error statement about Loop-back Operation of transceiver Table- 1 et4U.
com DataShee DataSheet4U.
com Revision History DataSheet...


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