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CY7C460A

Cypress Semiconductor
Part Number CY7C460A
Manufacturer Cypress Semiconductor
Description Asynchronous/ Cascadable 8K/16K/32K/64K x9 FIFOs
Published Mar 27, 2005
Detailed Description 60A CY7C460A/CY7C462A CY7C464A/CY7C466A Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs Features • High-speed, low-po...
Datasheet PDF File CY7C460A PDF File

CY7C460A
CY7C460A

Overview
60A CY7C460A/CY7C462A CY7C464A/CY7C466A Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs Features • High-speed, low-power, first-in first-out (FIFO) memories • 8K x 9 FIFO (CY7C460A) • 16K x 9 FIFO (CY7C462A) • 32K x 9 FIFO (CY7C464A) • 64K x 9 FIFO (CY7C466A) • 10-ns access times, 20-ns read/write cycle times • High-speed 50-MHz read/write independent of depth/width • Low operating power — ICC= 60 mA • • • • • • • • • • • — ISB =8 mA Asynchronous read/write Empty and Full flags Half Full flag (in standalone mode) Retransmit (in standalone mode) TTL-compatible Width and Depth Expansion Capability 5V ± 10% supply PLCC, LCC, 300-mil and 600-mil DIP packaging Three-state outputs Pin compatible density upgrade to CY7C42X/46X family Pin compatible and functionally equivalent to IDT7205, IDT7206, IDT7207, IDT7208 Functional Description The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in first-out (FIFO) memories.
Each FIFO memory is organized such that the data is read in the same sequential order that it was written.
Full and Empty flags are provided to prevent overrun and underrun.
Three additional pins are also provided to facilitate unlimited expansion in width, depth, or both.
The depth expansion technique steers the control signals from one device to another by passing tokens.
The read and write operations may be asynchronous; each can occur at a rate of up to 50 MHz.
The write operation occurs when the Write (W) signal is LOW.
Read occurs when Read (R) goes LOW.
The nine data outputs go to the high-impedance state when R is HIGH.
A Half Full (HF) output flag is provided that is valid in the standalone (single device) and width expansion configurations.
In the depth expansion configuration, this pin provides the expansion out (XO) information that is used to tell the next FIFO that it will be activated.
In the standalone and width expansion configurations, a LOW on the Retransmit (RT) input causes th...


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