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CY7C1380BV25

Part Number	CY7C1380BV25
Manufacturer	Cypress Semiconductor
Description	512K x 36 / 1 Mb x 18 Pipelined SRAM
Published	Mar 27, 2005
Detailed Description	1CY7C1380BV25 PRELIMINARY CY7C1380BV25 CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • • • • • • • • • •...
Datasheet	CY7C1380BV25 PDF File

Overview

1CY7C1380BV25 PRELIMINARY CY7C1380BV25 CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM Features • • • • • • • • • • • Fast clock speed: 200,166, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.
0,3.
2, 3.
4, 3.
8, 4.
2 ns Optimal for depth expansion 2.
5V (±5%) Operation Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed WRITE CYCLE Burst control pins (interleaved or linear burst sequence) • Automatic power-down for portable applications • High-density, high-speed packages • JTAG boundary scan for BGA packaging version (CLK).
The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control in, and ADV), Write Enables (BWa, BWb, puts (ADSC, ADSP BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and Burst Mode Control (MODE).
The data (DQa,b,c,d) and the data parity (DQPa,b,c,d) outputs, enabled by OE, are also asynchronous.
DQa,b,c,d and DQPa,b,c,d apply to CY7C1380BV25 and DQa,b and DQPa,b apply to CY7C1382BV25.
a, b, c, d each are of 8 bits wide in the case of DQ and 1 bit wide in the case of DP .
Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins.
Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip to initiate self-timed WRITE cycle.
WRITE cycles can be one to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written.
BWa controls DQa and DQPa.
BWb controls DQb and DQPb.
BWc controls DQc and DQPd.
BWd controls DQd-DQd and DQPd.
BWa, BWb BWc, and BWd can be active only with BWE being LOW.
GW being LOW causes all bytes to be written.
WRITE pass-through capability allows writt...

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CY7C1380BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM - Cypress Semiconductor

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