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CXL1512M

Part Number	CXL1512M
Manufacturer	Sony Corporation
Description	CCD Delay Line for NTSC
Published	Mar 27, 2005
Detailed Description	CXL1512M CCD Delay Line for NTSC For the availability of this product, please contact the sales office. Description The ...
Datasheet	CXL1512M PDF File

Overview

CXL1512M CCD Delay Line for NTSC For the availability of this product, please contact the sales office.
Description The CXL1512M is an IC developed for use in conjunction with Y/C signal processing ICs for NTSC.
This CCD delay line provides the comb filter output for eliminating the chrominance signal cross talk and 1H delay output for luminance signals.
Features • Single power supply (5V) • Built-in quadruple progression PLL circuit • Built-in comb filter • 1H delay output • Built-in peripheral circuits • Positive phase signal input, positive phase signal output Functions • Comb filter output • 1H delay output for luminance signal • Clock driver • Autobias circuit • Input clamp circuit (for luminance signals) • Center bias circuit (for chrominance signals) • Sample-and-hold circuit • Quadruple progression PLL circuit • Clock buffer output circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD +6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD 500 mW Recommended Operating Voltage (Ta = 25°C) VDD 5V ± 5% Structure CMOS-CCD 24 pin SOP (Plastic) Sony reserves the right to change products and specifications without prior notice.
This information does not convey any license by any implication or otherwise under any patents or other right.
Application circuits shown, if any, are typical examples illustrating the operation of the devices.
Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1– E94803-ST CXL1512M Recommended Clock Conditions (Ta = 25*C) • Input clock amplitude VCLK 0.
3Vp-p to 1.
0Vp-p (0.
5Vp-p Typ.
) • Clock frequency fCLK 3.
579545MHz • Input clock waveform sine wave Input Signal Amplitude Vsig 350mVp-p (Typ.
), 575mVp-p (Max.
) Block Diagram and Pin Configuration (Top View) PCOUT C-OUT AB-C AB-P (NC) (NC) (NC) VCOIN Vss (IC) 24 23 22 21 20 19 18 17 16 15 14 13 PLL fsc buffer Timing D Output circuit (S/H) Auto...

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