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M2006-02

Part Number	M2006-02
Manufacturer	Integrated Circuit Solution Inc
Description	VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION
Published	Mar 30, 2005
Detailed Description	Integrated Circuit Systems, Inc. Product Brief M2006-02/-12 VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION PIN A...
Datasheet	M2006-02 PDF File

Overview

Integrated Circuit Systems, Inc.
Product Brief M2006-02/-12 VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION PIN ASSIGNMENT (9 x 9 mm SMT) FIN_SEL1 GND FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 VCC DNC DNC DNC NC or APC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC GENERAL DESCRIPTION The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation.
They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming look-up tables.
The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.
813) MTIE and TDEV compliance during reference clock reselection.
Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected.
This phase-change triggered implementation of HS is not recommended when using an unstable reference (more than 1ns jitter pk-to-pk) or when the resulting phase detector frequency is less than 5MHz.
Refer to full product data sheet for more information.
27 26 25 24 23 22 21 20 19 28 29 30 31 32 33 34 35 36 M2006-02 M2006-12 (Top View) 18 17 16 15 14 13 12 11 10 P0_SEL P1_SEL nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND FEATURES • Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including: • 255/238 (OTU1) Mapping and 238/255 De-mapping • 255/237 (OTU2) Mapping and 237/255 De-mapping • 255/236 (OTU3) Mapping and 236/255 De-mapping Example I/O Clock Frequency Combinations Using M2006-02/-12-622.
0800 and Inverse FEC Ratios FEC PLL Ratio Mfec / Rfec 1/1 238/255 237/255 236/255 Base Input Rate 1 (MHz) 622.
0800 666.
5143 669.
3266 672.
1627 Output Clock (either output) MHz 622.
08 or 155.
52 • Supports input reference and VCSO frequencies up • • • • • to 700MHz, supports loop timing modes (Specify VCSO frequency at time of order) Low phase jitter < 0.
5 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz...

Similar Datasheet

M2006-02 VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION - Integrated Circuit Solution Inc
M2006-12 VCSO BASED FEC CLOCK PLL / HITLESS SWITCHING OPTION - Integrated Circuit Solution Inc
M2006-12A VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING - Integrated Circuit Systems

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