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M25P10

STMicroelectronics
Part Number M25P10
Manufacturer STMicroelectronics
Description 1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface
Published Apr 1, 2005
Detailed Description M25P10 1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface PRELIMINARY DATA s s s s s s s s s s s...
Datasheet PDF File M25P10 PDF File

M25P10
M25P10

Overview
M25P10 1 Mbit Low Voltage Paged Flash Memory With 20 MHz Serial SPI Bus Interface PRELIMINARY DATA s s s s s s s s s s s s s 1 Mbit PAGED Flash Memory 128 BYTE PAGE PROGRAM IN 3 ms TYPICAL 256 Kbit SECTOR ERASE IN 1 s TYPICAL BULK ERASE IN 2 s TYPICAL SINGLE 2.
7 V to 3.
6 V SUPPLY VOLTAGE SPI BUS COMPATIBLE SERIAL INTERFACE 20 MHz CLOCK RATE AVAILABLE SUPPORTS POSITIVE CLOCK SPI MODES DEEP POWER DOWN MODE (1 µA TYPICAL) ELECTRONIC SIGNATURE 10,000 ERASE/PROG CYCLES PER SECTOR 20 YEARS DATA RETENTION –40 TO 85°C TEMPERATURE RANGE 8 1 SO8 (MN) 150 mil width 8 1 SO8 (MW) 200 mil width DESCRIPTION The M25P10 is an 1 Mbit Paged Flash Memory fabricated with STMicroelectronics High Endurance CMOS technology.
The memory is accessed by a simple SPI bus compatible serial interface.
The bus signals are a serial clock input (C), a serial data input (D) and a serial data output (Q).
The device connected to the bus is selected when the chip select input (S) goes low.
Data is clocked in during the low to high transition of clock C, data Figure 1.
Logic Diagram VCC Table 1.
Signal Names C D Q Serial Clock Serial Data Input Serial Data Output Chip Select D C S W HOLD M25P10 Q S W HOLD VCC VSS Write Protect Hold Supply Voltage Ground VSS AI03744 June 2000 This is preliminary information on a new product now in development or undergoing evaluation.
Details are subject to change without notice.
1/21 M25P10 Figure 2.
SO Connections Chip Select (S) When S is high, the memory is deselected and the Q output pin is at high impedance and, unless an internal Read, Program, Erase or Write Status Register operation is underway, the device will be in the Standby Power mode (this is not the Deep Power Down mode).
S low enables the memory, placing it in the active power mode.
It should be noted that after power-on, a high to low transition on S is required prior to the start of any operation.
Hold (HOLD) The HOLD pin is used to pause serial communications with a SPI memory without res...


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