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DM74ALS169B

Fairchild Semiconductor
Part Number DM74ALS169B
Manufacturer Fairchild Semiconductor
Description Synchronous Four-Bit Up/Down Counters
Published Apr 1, 2005
Detailed Description DM74ALS169B Synchronous Four-Bit Up/Down Counters April 1984 Revised April 2000 DM74ALS169B Synchronous Four-Bit Up/Do...
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DM74ALS169B
DM74ALS169B

Overview
DM74ALS169B Synchronous Four-Bit Up/Down Counters April 1984 Revised April 2000 DM74ALS169B Synchronous Four-Bit Up/Down Counters General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications.
The DM74ALS169B is a four-bit binary up/ down counter.
The carry output is decoded to prevent spikes during normal mode of counting operation.
Synchronous operation is provided so that outputs change coincident with each other when so instructed by count enable inputs and internal gating.
This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters.
A buffered clock input triggers the four flip-flops on the rising (positive going) edge of clock input waveform.
These counters are fully programmable; that is, the outputs may each be preset either HIGH or LOW.
The load input circuitry allows loading with carry-enable output of cascaded counters.
As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating.
Both count enable inputs (P and T) must be LOW to count.
The direction of the count is determined by the level of the up/down input.
When the input is HIGH, the counter counts UP; when LOW, it counts DOWN.
Input T is fed forward to enable the carry outputs.
The carry output thus enabled will produce a low level output pulse with a duration approximately equal to the high portion of the QA output when counting UP, and approximately equal to the low portion of the QA when counting DOWN.
This low level overflow carry pulse can be used to enable successively cascaded stages.
Transitions at the enable P or T inputs are allowed regardless of the level of the clock input.
The control functions for these co...


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