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74ACT16541

Fairchild Semiconductor
Part Number 74ACT16541
Manufacturer Fairchild Semiconductor
Description 16-Bit Buffer/Line Driver
Published Apr 3, 2005
Detailed Description 74ACT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs August 1999 Revised October 1999 74ACT16541 16-Bit Buffer/Li...
Datasheet PDF File 74ACT16541 PDF File

74ACT16541
74ACT16541


Overview
74ACT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs August 1999 Revised October 1999 74ACT16541 16-Bit Buffer/Line Driver with 3-STATE Outputs General Description The ACT16541 contains sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver.
The device is byte controlled.
Each byte has separate 3-STATE control inputs which can be shorted together for full 16-bit operation.
Features s Separate control logic for each byte s Outputs source/sink 24 mA s TTL-compatible inputs Ordering Code: Order Number 74ACT16541SSC 74ACT16541MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.
300” Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), MO-153, 6.
1mm Wide Device also available in Tape and Reel.
Specify by appending suffix letter “X” to the ordering code.
Logic Symbol Connection Diagram Pin Descriptions Pin Names OEn I0–I15 O0–O15 Description Output Enable Input (Active LOW) Inputs Outputs FACT™ is a trademark of Fairchild Semiconductor Corporation © 1999 Fairchild Semiconductor Corporation DS500300 www.
fairchildsemi.
com 74ACT16541 Functional Description The ACT16541 contains sixteen non-inverting buffers with 3-STATE standard outputs.
The device is byte controlled with each byte functioning identically, but independent of the other.
The control pins can be shorted together to obtain full 16-bit operation.
The 3-STATE outputs are controlled by an Output Enable (OEn) input for each byte.
When OEn is LOW, the outputs are in 2-state mode.
When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.
Truth Tables Inputs OE1 L H X L OE2 L X H L Inputs OE3 L H X L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Outputs I0–I7 H X X L O0–O7 H Z Z L Outputs I8–I15 H X X L O8–O15 H Z Z L OE4 L X H L L...



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