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74AHC245

NXP
Part Number 74AHC245
Manufacturer NXP
Description Octal bus transceiver
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET 74AHC245; 74AHCT245 Octal bus transceiver; 3-state Product specification Supersedes data...
Datasheet PDF File 74AHC245 PDF File

74AHC245
74AHC245

Overview
INTEGRATED CIRCUITS DATA SHEET 74AHC245; 74AHCT245 Octal bus transceiver; 3-state Product specification Supersedes data of 1998 Sep 21 File under Integrated Circuits, IC06 1999 Sep 28 Philips Semiconductors Product specification Octal bus transceiver; 3-state FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have a Schmitt-trigger action • Inputs accepts voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and +125 °C.
DESCRIPTION The 74AHC/AHCT245 is a high-speed Si-gate CMOS device.
The 74AHC/AHCT245 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions.
The 74AHC245/74AHCT245 features an Output Enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.
OE controls the outputs so that the buses are effectively isolated.
Note 1.
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
FUNCTION TABLE See Note 1.
INPUTS OE L L H DIR L H X 74AHC245; 74AHCT245 INPUTS/OUTPUTS An A=B inputs Z Bn inputs B=A Z QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.
0 ns.
TYPICAL SYMBOL tPHL/tPLH CI CO CPD PARAMETER propagation delay An to Bn, Bn to An input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V 3.
5 AHCT 5.
0 3.
5 4.
0 15 ns pF pF pF UNIT VI = VCC or GND 3.
5 4.
0 12 Notes 1.
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts.
2.
The condition is VI = GND to VCC.
1999 Sep 28 2 Philips Semiconductors Pr...


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