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74ALS112A

NXP

Dual J-K negative edge-triggered flip-flop

INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook 1996 ...


NXP

74ALS112A

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INTEGRATED CIRCUITS 74ALS112A Dual J-K negative edge-triggered flip-flop Product specification IC05 Data Handbook 1996 June 27 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74ALS112A DESCRIPTION The 74ALS112A, dual negative edge-triggered JK-type flip-flop features individual J, K, clock (CPn), set (SD), and reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the function table regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CPn is High and the flip-flop will perform according to the function table as long as minimum setup and hold times are observed. Output changes are initiated by the High-to-Low transition of the CPn. TYPICAL SUPPLY CURRENT (TOTAL) 3.0mA PIN CONFIGURATION CP0 K0 J0 SD0 Q0 Q0 Q1 GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC RD0 RD1 CP1 K1 J1 SD1 Q1 SF00103 TYPE 74ALS112A TYPICAL fMAX 50MHz ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C 74ALS112AN 74ALS112AD DRAWING NUMBER 16-pin plastic DIP 16-pin plastic SO SOT38-4 SOT109-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS CP0, CP1 J0, J1 K0, K1 SD0, SD1 RD0, RD1 Q0, Q1, Q0, Q1 DESCRIPTION Clock Pulse input (active falling edge) J inputs K inpu...




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