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74ALVC162601

Fairchild Semiconductor
Part Number 74ALVC162601
Manufacturer Fairchild Semiconductor
Description Low Voltage 18-Bit Universal Bus Transceivers
Published Apr 3, 2005
Detailed Description 74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistor...
Datasheet PDF File 74ALVC162601 PDF File

74ALVC162601
74ALVC162601

Overview
74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.
6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the B-Port Outputs September 2001 Revised October 2001 74ALVC162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.
6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the B-Port Outputs General Description The 74ALVC162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs.
The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.
When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH-toLOW logic level.
If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB.
Output-enable OEAB is active-LOW.
When OEAB is HIGH, the outputs are in the HIGH-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA and CLKENBA.
The 74ALVC162601 is designed for low voltage (1.
65V to 3.
6V) VCC applications with I/O compatibility up to 3.
6V.
The 74ALVC162601 is also designed with 26Ω series resistors in the B-Port outputs.
This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.
Features I 1.
65V–3.
6V VCC supply operation I 3.
6V tolerant inputs and outputs I 26Ω series resistors in B-Port outputs I tPD (A to B) 4.
3 ns max for 3.
0V to 3.
6V VCC 5.
1 ns max for 2.
3V to 2.
7V VCC 9.
2 ns max for 1.
65V to 1.
95V VCC I Power-down high impedance inputs and outputs I Supports live insertion/withdrawal (Note 1) I Uses patented noise/EMI reduction circuitry I Latchup conforms to JEDEC JED78 I ESD performance: Human body model > 2000V Machine model >200V Note 1: To ens...


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