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74ALVT16601

NXP
Part Number 74ALVT16601
Manufacturer NXP
Description 18-bit universal bus transceiver
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS 74ALVT16601 18-bit universal bus transceiver (3-State) Product specification Supersedes data of 199...
Datasheet PDF File 74ALVT16601 PDF File

74ALVT16601
74ALVT16601

Overview
INTEGRATED CIRCUITS 74ALVT16601 18-bit universal bus transceiver (3-State) Product specification Supersedes data of 1996 Nov 14 IC23 Data Handbook 1998 Feb 13 Philips Semiconductors Philips Semiconductors Product specification 2.
5V/3.
3V 18-bit universal bus transceiver (3-State) 74ALVT16601 FEATURES • 18-bit bidirectional bus interface • 5V I/O Compatible • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up • Live insertion/extraction permitted • Power-up reset • Power-up 3-State • No bus current loading when output is tied to 5V bus • Positive edge triggered clock inputs • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model resistors to hold unused inputs DESCRIPTION The 74ALVT16601 is a high-performance BiCMOS product designed for VCC operation at 2.
5V and 3.
3V with I/O compatibility up to 5V.
This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs.
For A-to-B data flow, the device operates in the transparent mode when LEAB is High.
When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level.
If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB.
When OEAB is Low, the outputs are active.
When OEAB is High, the outputs are in the high-impedance state.
The clocks can be controlled with the clock-enable inputs (CEBA/CEAB).
Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
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