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74AUC1G00GV

NXP
Part Number 74AUC1G00GV
Manufacturer NXP
Description Single 2-input NAND gate
Published Apr 3, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET 74AUC1G00 Single 2-input NAND gate Preliminary specification File under Integrated Circu...
Datasheet PDF File 74AUC1G00GV PDF File

74AUC1G00GV
74AUC1G00GV

Overview
INTEGRATED CIRCUITS DATA SHEET 74AUC1G00 Single 2-input NAND gate Preliminary specification File under Integrated Circuits, IC24 2002 Nov 12 Philips Semiconductors Preliminary specification Single 2-input NAND gate FEATURES • Wide supply voltage range from 0.
8 to 2.
7 V • Performance optimised for VCC = 1.
8 V • High noise immunity • Complies with JEDEC standard: – JESD76 (1.
65 to 1.
95 V) • 8 mA output drive (VCC = 1.
65 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • ESD protection: 2000 V Human Body Model (A 114-A) 200 V Machine Model (A 115-A) • 3.
3 V tolerant inputs/outputs • SC-88A and SC-74A package.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; input slewrate ≥ 1 V/ns.
SYMBOL tPHL/tPLH PARAMETER propagation delay inputs A and B to output Y CONDITIONS VCC = 0.
8 V; CL = 15 pF; RL = 2 kΩ VCC = 1.
2 V; CL = 15 pF; RL = 2 kΩ VCC = 1.
5 V; CL = 15 pF; RL = 2 kΩ VCC = 1.
8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.
5 V; CL = 30 pF; RL = 500 Ω CI CPD Notes 1.
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts.
2.
The condition is VI = GND to VCC.
input capacitance power dissipation capacitance per buffer VCC = 1.
8 V; notes 1 and 2 DESCRIPTION 74AUC1G00 The 74AUC1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device.
Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.
This device is fully specified for partial power-down applications using Ioff.
The Ioff circuitry disables the output, preventing the damaging current backflow through the device when it is powered down.
The 74AUC1G00 provides the single 2-input NAND function.
TYPICAL 4.
7 1.
8 1.
4 1.
4 1.
2 4 14 ns ns ns ns ns UNIT pF pF 2002 Nov 12 2 Philips Semiconductors Preliminary specification Single 2-input NAND gate FUNCTION TABLE See note 1.
INPU...


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