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74AC573

STMicroelectronics
Part Number 74AC573
Manufacturer STMicroelectronics
Description OCTAL D-TYPE LATCH
Published Apr 3, 2005
Detailed Description 74AC573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s latch enable input (LE) and an output enab...
Datasheet PDF File 74AC573 PDF File

74AC573
74AC573

Overview
74AC573 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING s s s s s s latch enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q s outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be s latched precisely at the logic level of D input data.
While the (OE) input is low, the 8 outputs will be DESCRIPTION in a normal logic state (high or low logic level) The AC573 is an advanced high-speed CMOS www.
DataSheet4U.
com and while high level the outputs will be in a high OCTAL D-TYPE LATCH with 3 STATE OUTPUT impedance state.
NON INVERTING fabricated with sub-micron 2 All inputs and outputs are equipped with silicon gate and double-layer metal wiring C MOS protection circuits against static discharge, giving technology.
It is ideal for low power applications them 2KV ESD immunity and transient excess mantaining high speed operation similar to voltage.
equivalent Bipolar Schottky TTL.
These 8 bit D-Type latches are controlled by a s HIGH SPEED: tPD = 4.
5 ns (TYP.
) at VCC = 5V LOW POWER DISSIPATION: ICC = 8 µA (MAX.
) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.
) 50Ω TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 IMPROVED LATCH-UP IMMUNITY M B (Plastic Package) (Micro Package) ORDER CODES : 74AC573B 74AC573M PIN CONNECTION AND IEC LOGIC SYMBOLS April 1997 1/10 74AC573 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 NAME AND F UNCTIO N 3 State Output Enable Input (Active LOW) Data Inputs Q0 to Q7 3 State Latch Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage TRUTH TABLE INPUT S OE H L L L LE X L H H D X X L H OUT PUT S Q Z NO CHANGE * L H X: Don’t care Z: High i...


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