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74AC648

Fairchild Semiconductor
Part Number 74AC648
Manufacturer Fairchild Semiconductor
Description Octal Transceiver/Register
Published Apr 3, 2005
Detailed Description 74AC648 Octal Transceiver/Register with 3-STATE Outputs November 1988 Revised August 2000 74AC648 Octal Transceiver/Re...
Datasheet PDF File 74AC648 PDF File

74AC648
74AC648

Overview
74AC648 Octal Transceiver/Register with 3-STATE Outputs November 1988 Revised August 2000 74AC648 Octal Transceiver/Register with 3-STATE Outputs General Description The AC648 consists of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers.
Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA).
The four fundamental data handling functions available are illustrated in Figure 1, Figure 2, Figure 3, and Figure 4.
Features s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil slim dual-in-line package s Outputs source/sink 24 mA s Inverted data to output Ordering Code: Order Number 74AC648SC 74AC648SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.
300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.
300 Wide Device also available in Tape and Reel.
Specify by appending suffix letter “X” to the ordering code.
Logic Symbols Connection Diagram www.
DataSheet4U.
com IEEE/IEC Pin Descriptions Pin Names A0–A7 B0 – B7 CPAB, CPBA SAB, SBA DIR, G Description Data Register A Inputs, Data Register A 3-STATE Outputs Data Register B Inputs, Data Register B 3-STATE Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Inputs FACT is a trademark of Fairchild Semiconductor Corporation.
© 2000 Fairchild Semiconductor Corporation DS010133 www.
fairchildsemi.
com 74AC648 Function Table Inputs G H H H L L L L L L L L DIR X X X H H H H L L L L CPAB CPBA H or L H or L SAB X X X L L H H X X X X SBA X X X X X X X L L H H Output Input Input Input Input Data I/O (Note 1) A0–A7 B0–B7 Isolation Clock An Data into A Register Clock Bn Data into B Register An to Bn—Real Time (Transparent Mode) Output C...


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