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IDT74FCT163646

Integrated Device Technology
Part Number IDT74FCT163646
Manufacturer Integrated Device Technology
Description 3.3V CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS
Published Apr 4, 2005
Detailed Description 3.3V CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS Integrated Device Technology, Inc. IDT74FCT163646/A/C FEATURES: • 0.5 MICR...
Datasheet PDF File IDT74FCT163646 PDF File

IDT74FCT163646
IDT74FCT163646

Overview
3.
3V CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS Integrated Device Technology, Inc.
IDT74FCT163646/A/C FEATURES: • 0.
5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Packages include 25 mil pitch SSOP, 19.
6 mil pitch TSSOP and 15.
7 mil pitch TVSOP • Extended commercial range of -40°C to +85°C • VCC = 3.
3V ±0.
3V, Normal Range or VCC = 2.
7 to 3.
6V, Extended Range • CMOS power levels (0.
4µW typ.
static) • Rail-to-Rail output swing for increased noise margin • Low Ground Bounce (0.
3V typ.
) • Inputs (except I/O) can be driven by 3.
3V or 5V components DESCRIPTION: The FCT163646/A/C 16-bit registered transceivers are built using advanced dual metal CMOS technology.
These high-speed, low-power devices are organized as two independant 8-bit bus transceivers with 3-state D-type registers.
The control circuitry is organized for multiplexed transmission of data between A bus and B bus either directly or from the internal storage registers.
Each 8-bit transceiver/register features direction control (xDIR), over-riding Output Enable control (xOE) and Select lines (xSAB and xSBA) to select either real-time data or stored data.
Separate clock inputs are provided for A and B port registers.
Data on the A or B data bus, or both, can be stored in the internal registers by the LOW-to-HIGH transitions at the appropriate clock pins.
Flowthrough organization of signal pins simplifies layout.
All inputs are designed with hysteresis for improved noise margin.
The FCT163646/A/C have series current limiting resistors.
This offers low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB B REG 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB B REG D C 1A1 A REG 1B1 2A1 A REG D C 2B1 D C D C TO 7 OTHER CHANNELS 2778 drw 01 TO 7 OTHER CHANNELS 2778 drw 02 The IDT lo...


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