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ispGDX160V-7Q208

Lattice Semiconductor
Part Number ispGDX160V-7Q208
Manufacturer Lattice Semiconductor
Description In-System Programmable 3.3V Generic Digital CrosspointTM
Published Apr 5, 2005
Detailed Description ispGDX 160V/VA TM In-System Programmable 3.3V Generic Digital Crosspoint TM Features • IN-SYSTEM PROGRAMMABLE GENERIC ...
Datasheet PDF File ispGDX160V-7Q208 PDF File

ispGDX160V-7Q208
ispGDX160V-7Q208

Overview
ispGDX 160V/VA TM In-System Programmable 3.
3V Generic Digital Crosspoint TM Features • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation — Space-Saving PQFP and BGA Packaging — Dedicated IEEE 1149.
1-Compliant Boundary Scan Test • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.
3V Core Power Supply — 3.
5ns Input-to-Output/3.
5ns Clock-to-Output Delay* — 250MHz Maximum Clock Frequency* — TTL/3.
3V/2.
5V Compatible Input Thresholds and Output Levels (Individually Programmable)* — Low-Power: 16.
5mA Quiescent Icc* — 24mA IOL Drive with Programmable Slew Rate Control Option — PCI Compatible Drive Capability* — Schmitt Trigger Inputs for Noise Immunity — Electrically Erasable and Reprogrammable — Non-Volatile E2CMOS Technology • ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES — 3.
3V In-System Programmable Using Boundary Scan Test Access Port (TAP) — Change Interconnects in Seconds • FLEXIBLE ARCHITECTURE — Combinatorial/Latched/Registered Inputs or Outputs — Individual I/O Tri-state Control with Polarity Control — Dedicated Clock/Clock Enable Input Pins (four) or Programmable Clocks/Clock Enables from I/O Pins (40) — Single Level 4:1 Dynamic Path Selection (Tpd = 3.
5ns) — Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX — Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins — Outputs Tri-state During Power-up (“Live Insertion” Friendly) • DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE — MS Windows or NT / PC-Based or Sun O/S — Easy Text-Based Design Entry — Automatic Signal Routing — Program up to 100 ISP Devices Concurrently — Simulator Netlist Generation for Easy Board-Level Simulation * “VA” Version Only Functional Block Diagram I/O Pins D ISP Control I/O Pins C I/O Pins A I/O Cells Global Routing Pool (GRP) I/O Cel...


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