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ISPL1048E-100LQI

Part Number	ISPL1048E-100LQI
Manufacturer	Lattice Semiconductor
Description	High-Density Programmable Logic
Published	Apr 5, 2005
Detailed Description	ispLSI 1048E ® High-Density Programmable Logic Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pi...
Datasheet	ISPL1048E-100LQI PDF File

Overview

ispLSI 1048E ® High-Density Programmable Logic Features • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic — Functionally and Pin-out Compatible to ispLSI 1048C TECHNOLOGY • HIGH PERFORMANCE — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.
5 ns Propagation Delay — TTL Compatible Inputs and Outputs — Electrically Eraseable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture • IN-SYSTEM PROGRAMMABLE — In-System Programmable (ISP™) 5V Only — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Four Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispLSI DEVELOPMENT TOOLS ispVHDL™ Systems — VHDL/Verilog-HDL/Schematic Design Options — Functional/Timing/VHDL Simulation Options ispDS+™ VHDL Synthesis-Optimized Logic Fitter — Supports Leading Third-Party Design Environments for Schematic Capture, Synthesis and Timing Simulation — Static Timing Analyzer ispDS™ Software — Lattice HDL or Boolean Logic Entry — Functional Simulator and Waveform Viewer ISP Daisy Chain Download Software E2CMOS® Functional Block Diagram Output Routing Pool F7 F6 F5 F4 F3 F2 F1 F0 A0 Output Routing Pool Output Routing Pool E7 E6 E5 E4 E3 E2 E1 E0 D7 D5 Output Routing Pool 0139G1A-isp D Q A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 Output Routing Pool D6 Logic D Q Global Routi...

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