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ISPLSI2128VE

Lattice Semiconductor
Part Number ISPLSI2128VE
Manufacturer Lattice Semiconductor
Description 3.3V In-System Programmable SuperFAST High Density PLD
Published Apr 5, 2005
Detailed Description ispLSI 2128VE 3.3V In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRA...
Datasheet PDF File ISPLSI2128VE PDF File

ISPLSI2128VE
ISPLSI2128VE


Overview
ispLSI 2128VE 3.
3V In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2128V Devices • 3.
3V LOW VOLTAGE 2128 ARCHITECTURE — Interfaces with Standard 5V TTL Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 250MHz Maximum Operating Frequency — tpd = 4.
0ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 3.
3V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of WiredOR Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.
1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms ® Functional Block Diagram* Output Routing Pool (ORP) D7 D6 D5 D4 Output Routing Pool (ORP) D3 D2 D1 D0 C7 Output Routing Pool (ORP) A0 A1 C6 A2 D Q C...


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