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IDT71F432

Part Number	IDT71F432
Manufacturer	Integrated Device Technology
Description	32k X 32 mcACHE synchronous pipelined cache ram
Published	Apr 5, 2005
Detailed Description	Integrated Device Technology, Inc. 32K x 32 MCache SYNCHRONOUS PIPELINED CACHE RAM IDT71F432 FEATURES: • • • • • • • ...
Datasheet	IDT71F432 PDF File

Overview

Integrated Device Technology, Inc.
32K x 32 MCache SYNCHRONOUS PIPELINED CACHE RAM IDT71F432 FEATURES: • • • • • • • • • • Uses IDT's Fusion Memory technology 66 and 75 MHz speed grades 3-1-1-1 Pipelined Burst Read 3-1-1-1 Pipelined Burst Write 3-1-1-1-1-1-1-1.
.
.
extended pipelined operation Refresh overhead consumes less than 0.
5% of cycles Pinout is superset of industry standard PBSRAM Interchangeable with PBSRAM in new designs Compatible with MoSys MCache™ devices Low operating and standby power consumption 1/3 the power of standard PBSRAM • Packaged in a JEDEC Standard 100-pin rectangular plastic thin quad flatpack (TQFP) DESCRIPTION: The IDT71F432 MCache is a high-performance, low-power replacement for standard 32K x 32 pipelined burst SRAM (PBSRAM) in cache applications.
The 71F432 is built using IDT's Fusion Memory technology, which combines the performance of SRAM with the cost structure of DRAM.
It is fundamentally compatible with standard PBSRAM, with additional features to accommodate the internal DRAM operation of the memory.
These additional features are defined so that 71F432 compatible system controllers and properly implemented PC boards can work transparently with either the 71F432 or PBSRAM in cache memory applications.
Six pins, identified as No Connect (NC) on the standard PBSRAM specifications, are used to support 71F432 operation.
These pins are 5V supply (2), host bus W/R#, RESET# and two proprietary functions labeled F0 and F1.
When using standard PBSRAM, these pins have no effect and the associated functions in the 71F432-compatible chipset are not activated.
The 71F432 supports PBSRAM operating modes, including burst read (3-1-1-1), burst write (3-1-1-1) and pipelined burst read or write (3-1-1-1-1-1.
.
.
).
As with all DRAM devices, refresh is required.
The memory is not accessible during the refresh interval.
Refresh occupies 0.
5% of the clock cycles, resulting in a system performance reduction of less than 0.
1%.
ABOUT IDT'S Fusion Mem...

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IDT71F432 32k X 32 mcACHE synchronous pipelined cache ram - Integrated Device Technology

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