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S3C7559

Part Number	S3C7559
Manufacturer	Samsung semiconductor
Description	single-chip CMOS microcontroller
Published	Apr 7, 2005
Detailed Description	S3C7559/P7559 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVERVIEW The S3C7559/P7559 single-chip CMOS microcontroller has be...
Datasheet	S3C7559 PDF File

Overview

S3C7559/P7559 PRODUCT OVERVIEW 1 PRODUCT OVERVIEW OVERVIEW The S3C7559/P7559 single-chip CMOS microcontroller has been designed for high-performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).
The S3P7559 is a microcontroller which has 32-kbyte one-time-programmable EPROM but its functions are same to S3C7559.
With its DTMF generator, 8-bit serial I/O interface, and versatile 8-bit timer/counters, the S3C7559/P7559 offers an excellent design solution for a wide variety of telecommunication applications.
Up to 55 pins of the 64-pin SDIP or QFP package can be dedicated to I/O.
Seven vectored interrupts provide fast response to internal and external events.
In addition, the S3C7559/P7559's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
DEVELOPMENT SUPPORT The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for S3C7-series microcontrollers that is powerful, reliable, and portable.
In addition to its window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications.
The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats.
SAMA generates industry-standard hex files that also contain program control data for SMDS compatibility.
1-1 PRODUCT OVERVIEW S3C7559/P7559 FEATURES SUMMARY Memory • • Bit Sequential Carrier • 1 K × 4-bit RAM 32 K × 8-bit ROM Supports 8-bit serial data transfer in arbitrary format 55 I/O Pins • • • Interrupts • • • Input only: 4 pins I/O: 43 pins N-channel open-drain I/O (S/W): 8 pins 3 external interrupt vectors 4 internal interrupt vectors 2 quasi-interrupts Memory-Mapped I/O Structure • Power-Down Modes • • Data memory bank 15 Idle: Only CPU clock stops Stop: Main system ...

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