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S5F325NU02

Samsung semiconductor
Part Number S5F325NU02
Manufacturer Samsung semiconductor
Description 1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA
Published Apr 7, 2005
Detailed Description 1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA S5F325NU02 INTRODUCTION The S5F325NU02 is an interline transfer CCD area imag...
Datasheet PDF File S5F325NU02 PDF File

S5F325NU02
S5F325NU02

Overview
1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA S5F325NU02 INTRODUCTION The S5F325NU02 is an interline transfer CCD area image sensor developed for EIA 1/3 inch optical format video cameras, surveillance cameras, object detectors and image pattern recognizers.
High sensitivity is achieved through the on-chip micro lenses and HAD (Hole Accumulated Diode) photosensors.
This chip features a field integration read out system and an electronic shutter with variable charge storage time.
16Pin Cer-DIP FEATURES • • • • • • • High Sensitivity Optical Size 1/3 inch Format Low Dark Current Horizontal Register 5V Drive 16pin Ceramic DIP Package Field Integration Read Out System No DC Bias on Reset Gate ORDERING INFORMATION Device S5F325NU02-LAB0 Package 16Pin Cer - DIP Operating -10 °C − +60 °C STRUCTURE • • • • • Number of Total Pixels: Number of Effective Pixels: Chip Size: Unit Pixel Size: Optical Blacks & Dummies: 537(H) × 505(V) 510(H) × 492(V) 6.
00mm(H) × 4.
95mm(V) 9.
60 µm(H) × 7.
50 µm(V) Refer to Figure Below Vertical 1 Line (Even Field Only) 16 2 510 25 1 Dummy Pixels Optical Black Pixels Effective Imaging Area OUTPUT V-CCD 492 12 Effective Pixels H-CCD 1 S5F325NU02 1/3 INCH CCD IMAGE SENSOR FOR EIA CAMERA BLOCK DIAGRAM (Top View) 8 VOUT 7 VSS 6 VGG 5 GND ΦV1 4 ΦV2 3 ΦV3 2 ΦV4 1 Vertical Shift Register CCD Vertical Shift Register CCD Vertical Shift Register CCD Horizontal Shift Register CCD Vertical Shift Register CCD 9 VDD 10 GND 11 SUB 12 VL ΦRS 13 14 NC ΦH1 15 ΦH2 16 Figure 1.
Block Diagram PIN DESCRIPTION Table 1.
Pin Description Pin 1 2 3 4 5 6 7 8 Symbol ΦV4 ΦV3 ΦV2 ΦV1 GND VGG VSS VOUT Description Vertical CCD transfer clock 4 Vertical CCD transfer clock 3 Vertical CCD transfer clock 2 Vertical CCD transfer clock 1 Ground Output stage gate bias Output stage source bias Signal output Pin 9 10 11 12 13 14 15 16 Symbol VDD GND SUB VL ΦRS NC ΦH1 ΦH2 Description Output stage drain bias Ground Substrate bias Protection circuit...


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